The present invention relates to communication between hardware entities in an integrated circuit, and more specifically, to assigning and monitoring managed addresses assigned to a system bus in the integrated circuit.
Processors may include multiple cores that are used to perform instructions. These cores may be interconnected within the processor using a system bus (also referred to as a processor bus). In some processors, the system bus communicatively couples the cores to one or more accelerators in the processor which perform specialized tasks such as data compression or encoding/decoding of information (i.e., cryptography). Managing the flow of data between the cores and the accelerators via the system bus is an important performance metric of the processor.